Details
- IBM and Lam Research announced a five-year agreement on March 10, 2026, to develop processes and materials for sub-1nm logic scaling, focusing on novel materials, fabrication processes, and High-NA EUV lithography.
- Key figures include Mukesh Khare, GM of IBM Semiconductors and VP of Hybrid Cloud at IBM Research, and Vahid Vahedi, Chief Technology and Sustainability Officer at Lam Research.
- The collaboration leverages IBM's Albany NanoTech Complex and Lam's tools like Aether dry resist, Kiyo and Akara etch platforms, and Striker and ALTUS deposition systems to validate flows for nanosheet, nanostack devices, and backside power delivery.
- Builds on over a decade of partnership enabling 7nm, nanosheet, EUV technologies, and IBM's 2021 2nm chip; extends to complex 3D architectures amid industry shift to High-NA EUV.
- Recent IBM SPIE 2026 presentations confirm High-NA EUV progress for below-2nm nodes, with partners like ASML and Lam accelerating lithography and patterning innovations.
Impact
This partnership positions IBM and Lam to lead sub-1nm scaling, critical for AI-driven demand for denser, lower-power chips. It counters challenges in 3D architectures and High-NA EUV adoption, potentially accelerating industry timelines versus competitors like TSMC or Intel. Success could enhance U.S. semiconductor sovereignty and boost Lam's equipment dominance in advanced nodes.
