Details
- IBM introduced a sub-1 nanometer chip technology at the 0.7 nm (7 angstrom) node, claiming nearly 100 billion transistors on a fingernail-sized chip and projecting up to 50% higher performance or 70% greater energy efficiency versus its 2 nm node announced in 2021.
- The breakthrough is built on IBM’s new "nanostack" architecture, described as the industry’s first known three-dimensional, nanosheet-based transistor design that vertically stacks and staggers transistors using 3D sequential integration.
- Nanostack allows different channel materials in each stacked layer and has been experimentally validated via ultra-thin dielectric wafer bonding, dual-channel engineering, and functional CMOS inverter operation; IBM also reports a 40% SRAM scaling improvement supporting high-bandwidth AI workloads.
- The work extends logic technology below the 1 nm node into angstrom-level scaling and aligns with IBM’s broader semiconductor roadmap, which leverages High NA EUV lithography at the Albany Nanotech Complex and collaborations with Lam Research, Tokyo Electron, and SCREEN for process development.
- IBM positions this as a decade-long scaling path for silicon and links it to its wider strategy, including the planned Anderon quantum foundry aimed at U.S.-based quantum wafer manufacturing and future adoption of nanostack in production within about five years.
Impact
This announcement directly addresses concerns over the slowing of Moore’s Law by demonstrating viable angstrom-scale logic and memory scaling, critical for AI data centers and advanced edge devices. If nanostack transitions from lab to foundry within 5–10 years, it could reshape high-performance computing roadmaps, accelerate AI and quantum hardware co-design, and intensify competition and capital investment around High NA EUV and 3D transistor architectures.
