Details
- AMD began production ramp of its 6th Gen EPYC data center CPU, codenamed "Venice," manufactured on TSMC's advanced 2nm process in Taiwan, with plans to later ramp at TSMC's Arizona fab.
- The announcement highlights AMD's partnership with TSMC, with comments from AMD CEO Dr. Lisa Su and TSMC CEO Dr. C.C. Wei underscoring joint efforts on leading-edge CPU and packaging technologies.
- "Venice" is described as the first high-performance computing product to reach production ramp on TSMC's 2nm node, targeting next-generation cloud, enterprise, HPC and AI infrastructure, especially agentic AI workloads.
- AMD also disclosed "Verano," a follow-on 6th Gen EPYC CPU on TSMC 2nm optimized for performance-per-dollar-per-watt and featuring integrated LPDDR to address growing memory and efficiency demands in cloud and AI deployments.
- The company is expanding its geographically diverse manufacturing footprint and leveraging TSMC's SoIC-X and CoWoS-L advanced packaging to deliver more integrated, scalable AI and data center platforms across its CPU and broader AI portfolio.
Impact
Bringing a 2nm data center CPU into production squarely positions AMD in the next phase of AI and cloud infrastructure, where power efficiency and memory bandwidth are critical constraints. Over the next 12–24 months, Venice and Verano could shift data center CPU design priorities toward tighter CPU-memory integration and more diverse manufacturing geographies, intensifying competition with Intel and ARM-based server ecosystems in AI-centric workloads.
